The present invention relates in general to electronic remote wireless communication devices and, more particularly, to a frequency synthesizer controller incorporated with a serial peripheral interface.
In wireless communications, for example using pagers, cellular phones, and two-way radios, messages are transmitted between a base station and a remote unit, or between two or more remote units. In a pager application, the base station transmits a message to the pager. The pager notifies the user that a message has been received and upon user command displays the message on a display screen.
A typical configuration of a remote wireless communication device, e.g. a pager, includes a receiver section for receiving, downconverting, and demodulating the transmitted message to baseband data. The pager must operate over a variety of transmission frequencies as it roams from one operating area to another. Consequently, the receiver section uses a frequency synthesizer to programmably set the reference frequency to the receiver section. A central processing unit (CPU) or other microcontroller with associated memory communicates over a peripheral bus through a serial peripheral interface (SPI) to a message control block. The message control block receives messages from the receiver section. The message control block passes the messages through the SPI to the CPU for processing and display. The CPU also communicates over the peripheral bus through another SPI to enable, disable, and set the operating frequency of the frequency synthesizer. A system clock generator using a phase lock loop (PLL) provides system clock signals to operate the pager.
Most if not all pagers receive operating power from a battery source. Power conservation is an important design consideration to maximize battery life. In the prior art, the message control block is initialized to have prior knowledge of the communication protocol in effect for the present operating or roaming area. According to the communication protocol, the pager receives messages during a narrow predefined window reoccurring at a known cycle. The receive message window reoccurs at a rate ranging between about every two seconds to about every four minutes. The CPU, memory, PLL, SPI, message control block, frequency synthesizer, and receiver section are operating during the window in order to monitor, receive, and process any messages. After the receive message window, the CPU, memory, PLL, SPI, frequency synthesizer, and receiver section are typically disabled or put to sleep to conserve power. The message control block remains active to maintain timing of the arrival of the receive message windows. Just prior to the receive message window, the message control block sends an interrupt via an interrupt controller to awake the CPU, memory, PLL, and SPI blocks. The CPU sends commands via the SPIs to enable the frequency synthesizer and receiver section to be ready for any incoming messages.
Considerable power is required to awaken and operate the CPU, memory, PLL, SPI, frequency synthesizer, and receiver section to monitor for received messages, especially for communication protocols that use frequent receive message windows, e.g. every two seconds.
Thus, there is a need to reduce power consumption in remote wireless communication devices during times of monitoring for incoming communications.